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EP2S60F1020I4N 500mA 718 I/O Stratix II

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EP2S60F1020I4N 500mA 718 I/O Stratix II

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Brand Name :	Intel / Altera
Model Number :	EP2S60F1020I4N
Certification :	Lead free / RoHS Compliant
Price :	USD 2000-3000 pcs
Payment Terms :	T/T, Western Union, Paypal, Trade Assurance, Credit Card
Supply Ability :	448 pcs
Delivery Time :	3-5 Day

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EP2S60F1020I4N 500mA 718 I/O Stratix II

EP2S60F1020I4N ALTERA FPGA Chip FBGA-1020 718 I/O Stratix II

Product Attribute	Attribute Value
Manufacturer:	Intel
Product Category:	FPGA - Field Programmable Gate Array
Product:	Stratix II
Number of Logic Elements:	60440
Number of Logic Array Blocks - LABs:	3022
Number of I/Os:	718 I/O
Operating Supply Voltage:	1.2 V
Minimum Operating Temperature:	- 40 C
Maximum Operating Temperature:	+ 85 C
Mounting Style:	SMD/SMT
Package / Case:	FBGA-1020
Packaging:	Tray
Series:	Stratix II EP2S60
Brand:	Intel / Altera
Moisture Sensitive:	Yes
Operating Supply Current:	500 mA
Product Type:	FPGA - Field Programmable Gate Array
Factory Pack Quantity:	24
Subcategory:	Programmable Logic ICs
Total Memory:	2544192 bit
Tradename:	Stratix II
Part # Aliases:	973068

Stratix® II devices contain a two-dimensional row- and column-based architecture to implement custom logic. A series of column and row
interconnects of varying length and speed provides signal interconnects between logic array blocks (LABs), memory block structures (M512 RAM,
M4K RAM, and M-RAM blocks), and digital signal processing (DSP) blocks.

Each LAB consists of eight adaptive logic modules (ALMs). An ALM is the Stratix II device family’s basic building block of logic providing
efficient implementation of user logic functions. LABs are grouped into rows and columns across the device.

M512 RAM blocks are simple dual-port memory blocks with 512 bits plus parity (576 bits). These blocks provide dedicated simple dual-port or
single-port memory up to 18-bits wide at up to 500 MHz. M512 blocks are grouped into columns across the device in between certain LABs.

■ High-speed differential I/O support with DPA circuitry for 1-Gbps performance
■ Support for high-speed networking and communications bus standards including Parallel RapidIO, SPI-4 Phase 2 (POS-PHY Level 4), HyperTransport™ technology, and SFI-4
■ Support for high-speed external memory, including DDR and DDR2 SDRAM, RLDRAM II, QDR II SRAM, and SDR SDRAM
■ Support for design security using configuration bitstream encryption
■ Support for remote configuration updates
■ Up to 16 global clocks with 24 clocking resources per device region
■ Clock control blocks support dynamic clock network enable/disable, which allows clock networks to power down to reduce power consumption in user mode

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