• TSMC's 20-nm SoC process technology
• Allows operation at a lower VCC level of 0.82 V instead of the 0.9 V standard VCC core voltage
• 1.0 mm ball-pitch Fineline BGA packaging
• 0.8 mm ball-pitch Ultra Fineline BGA packaging
• Multiple devices with identical package footprints for seamless migration between different FPGA densities
• Devices with compatible package footprints allow migration to next generation high-end Stratix® 10 devices
• RoHS, leaded(1), and lead-free (Pb-free) options
• Enhanced 8-input ALM with four registers
• Improved multi-track routing architecture to reduce congestion and improve compilation time
• Hierarchical core clocking architecture
• Fine-grained partial reconfiguration
• M20K—20-Kb memory blocks with hard error correction code (ECC)
• Memory logic array block (MLAB)—640-bit memory
• Native support for signal processing precision levels from 18 x 19 to 54 x 54
• Native support for 27 x 27 multiplier mode
• 64-bit accumulator and cascade for systolic finite impulse responses (FIRs)
• Internal coefficient memory banks
• Preadder/subtractor for improved efficiency
• Additional pipeline register to increase performance and reduce power

• Supports floating point arithmetic:
— Perform multiplication, addition, subtraction, multiply-add, multiply-subtract, and complex multiplication.
— Supports multiplication with accumulation capability, cascade summation, and cascade subtraction capability.
— Dynamic accumulator reset control.
— Support direct vector dot and complex multiplication chaining multiply floating point DSP blocks.