Virtex-5 devices are user-programmable gate arrays with various configurable elements and embedded cores optimized for high-density and high-performance system designs. Virtex-5 devices implement the following functionality:

• I/O blocks provide the interface between package pins and the internal configurable logic. Most popular and
leading-edge I/O standards are supported by programmable I/O blocks (IOBs). The IOBs can be connected to
very flexible ChipSync logic for enhanced source-synchronous interfacing. Source-synchronous optimizations
include per-bit deskew (on both input and output signals), data serializers/deserializers, clock dividers, and
dedicated I/O and local clocking resources.

• Configurable Logic Blocks (CLBs), the basic logic elements for Xilinx® FPGAs, provide combinatorial and
synchronous logic as well as distributed memory and SRL32 shift register capability. Virtex-5 FPGA CLBs
are based on real 6-input look-up table technology and provide superior capabilities and performance
compared to previous generations of programmable logic.

• Cascadable embedded DSP48E slices with 25 x 18 two’s complement multipliers and 48-bit
adder/subtracter/accumulator provide massively parallel DSP algorithm support. In addition, each
DSP48E slice can be used to perform bitwise logical functions.